module DA(
input clk,
input rst,
output wire scl_receive,
inout wire sda_receive,
// output wire [7:0] data_out,
output wire scl_send,
inout wire sda_send
);

parameter sec = 1;

wire [7:0] data_out;
wire [7:0] data;
wire [7:0] data1;
(* preserve *) reg clk_div_dbg;
(* preserve *) reg [7:0] data_dbg;

wire clk_div;
assign data_out = sec ? data : data1 ;


always @(*) begin
clk_div_dbg <=  clk_div;
end
always @(*)begin
data_dbg <= data_out;
end

converter u_converter(
.clk (clk),
.rst (rst),
.data (data),
.data1 (data1),
.clk_div (clk_div)
);

vga u_vga(
.sys_clk (clk),
.sys_rst_n (rst),
.ram_clk (clk_64),
.ram_data (show_data)
);

i2c_dri u_i2c_dri_send(
.clk (clk),
.rst_n (rst),
.i2c_exec (1'b1),
.i2c_rh_wl (1'b0),
.i2c_addr (8'b01000000),
.i2c_data_w (data_out),
.scl (scl_send),
.sda (sda_send)
);

i2c_dri u_i2c_dri_receive(
.clk (clk),
.rst_n (rst),
.i2c_exec (1'b1),
.i2c_rh_wl (1'b1),
.i2c_addr (8'b00000011),
.i2c_data_r (show_data),
.scl (scl_receive),
.sda (sda_receive)
);
endmodule